Search - vhdl encoder

[Other resource] VHDL范例

Description: 最高优先级编码器 8位相等比较器三人表决器（三种不同的描述方式）加法器描述 8位总线收发器：74245 （注2）地址译码（for m68008）多路选择器（使用select语句） LED七段译码多路选择器（使用if－else语句）双2－4译码器：74139 多路选择器（使用when－else语句）二进制到BCD码转换多路选择器（使用case语句）二进制到格雷码转换双向总线（注2）汉明纠错吗译码器三态总线（注2）汉明纠错吗编码器解复用器 -highest priority encoder, compared to eight for phase three of the vote (the description of three different ways) Adder Description eight bus Transceivers : 74,245 (Note 2) address decoder (for m68008) Multiple choice (use select statement) LED paragraph 107 of decoding multiple choice ( use if-else statements) 2-4 dual decoder : over 74,139 road choice (use when-else statements) of the binary conversion BCD multiple choice (use case statement) binary Gray code conversion to a two-way bus (Note 2)? Hamming error correction decoder three-state Bus (Note 2)? Hamming error correction encoder demultiplexer
Platform: | Size: 42884 | Author: kerty | Hits:

[Other resource] encoder

Description: VHDL实现循环码编码，设计了三个单元。switch是一个开关，shifter是移位寄存器，encoder是主体。
Platform: | Size: 1943 | Author: 王三一 | Hits:

[VHDL-FPGA-Verilog] simple h264 vhdl encoder

Description: simple h264 encoder，source code and test code in vhdl，简单h264 硬件编码器，源代码及测试，vhdl语言
Platform: | Size: 399279 | Author: lida1204@gmail.com | Hits:

[SCM] VHDL范例

Description: 最高优先级编码器 8位相等比较器三人表决器（三种不同的描述方式）加法器描述 8位总线收发器：74245 （注2）地址译码（for m68008）多路选择器（使用select语句） LED七段译码多路选择器（使用if－else语句）双2－4译码器：74139 多路选择器（使用when－else语句）二进制到BCD码转换多路选择器（使用case语句）二进制到格雷码转换双向总线（注2）汉明纠错吗译码器三态总线（注2）汉明纠错吗编码器解复用器 -highest priority encoder, compared to eight for phase three of the vote (the description of three different ways) Adder Description eight bus Transceivers : 74,245 (Note 2) address decoder (for m68008) Multiple choice (use select statement) LED paragraph 107 of decoding multiple choice ( use if-else statements) 2-4 dual decoder : over 74,139 road choice (use when-else statements) of the binary conversion BCD multiple choice (use case statement) binary Gray code conversion to a two-way bus (Note 2)? Hamming error correction decoder three-state Bus (Note 2)? Hamming error correction encoder demultiplexer
Platform: | Size: 43008 | Author: kerty | Hits:

[VHDL-FPGA-Verilog] encoder

Description: VHDL实现循环码编码，设计了三个单元。switch是一个开关，shifter是移位寄存器，encoder是主体。-VHDL realization of cyclic code encoding, designed three modules. switch is a switch, shifter is the shift register, encoder is the main.
Platform: | Size: 2048 | Author: 王三一 | Hits:

[VHDL-FPGA-Verilog] mancheester_v

Description: 用Verilog HDL实现的曼彻斯特编码器和解码器。-Using Verilog HDL realize the Manchester encoder and decoder.
Platform: | Size: 9216 | Author: wangyunshann | Hits:

[SCM] CPLD

Description: 控制三相步进电机及光电编码器的采集,当电机停止时,保证三相里面只有一相相通,防止停止时电流过大.-Control three-phase stepper motor and optical encoder collection, when the motor stops to ensure that only one phase of three-phase inside the heart, and to prevent too much current is stopped.
Platform: | Size: 580608 | Author: suifeg | Hits:

[VHDL-FPGA-Verilog] vhdl

Description: 最高优先级编码器和直流电机控制器,供初学者学习使用，方便快捷，有很强的参考价值-The highest priority encoder and DC motor controller, for beginners learning to use, convenient and has a strong reference value
Platform: | Size: 3072 | Author: 张楚荀 | Hits:

[VHDL-FPGA-Verilog] CRC16bits

Description: 16bit crc encoder ande demo
Platform: | Size: 167936 | Author: chen | Hits:

[VHDL-FPGA-Verilog] s3esk_rotary_encoder_interface

Description: Xilix spartan 3E 旋转编码器接口,脉冲方向识别,AB脉冲滤波 Rotary Encoder Interface Demonstrates how to use the rotary encoder portion of the rotary pushbutton switch.-Xilix spartan 3E rotary encoder interface, pulse direction identification, AB pulse filter Rotary Encoder InterfaceDemonstrates how to use the rotary encoder portion of the rotary pushbutton switch.
Platform: | Size: 279552 | Author: weihua yuan | Hits:

[source in ebook] HammingDecoder

Description: -- Hamming Decoder -- This Hamming decoder accepts an 8-bit Hamming code (produced by the encoder above) and performs single error correction and double error detection. -- download from: www.pld.com.cn & www.fpga.com.cn LIBRARY ieee USE ieee.std_logic_1164.ALL ENTITY hamdec IS PORT(hamin : IN BIT_VECTOR(0 TO 7) --d0 d1 d2 d3 p0 p1 p2 p4 dataout : OUT BIT_VECTOR(0 TO 3) --d0 d1 d2 d3 sec, ded, ne : OUT BIT) --diagnostic outputs END hamdec ARCHITECTURE ver1 OF hamdec IS BEGIN --- Hamming Decoder -- This Hamming decoder accepts an 8-bit Hamming code (produced by the encoder above) and performs single error correction and double error detection. -- download from: www.pld.com.cn & www.fpga.com.cn LIBRARY ieee USE ieee.std_logic_1164.ALL ENTITY hamdec IS PORT(hamin : IN BIT_VECTOR(0 TO 7) --d0 d1 d2 d3 p0 p1 p2 p4 dataout : OUT BIT_VECTOR(0 TO 3) --d0 d1 d2 d3 sec, ded, ne : OUT BIT) --diagnostic outputs END hamdec ARCHITECTURE ver1 OF hamdec IS BEGIN
Platform: | Size: 4096 | Author: djs | Hits:

[VHDL-FPGA-Verilog] mux4

Description: 四位乘法器的VHDL语言设计，并有原理图的描述-4 Multiplier VHDL language design, and schematic description of
Platform: | Size: 203776 | Author: 望天 | Hits:

[VHDL-FPGA-Verilog] vhdl-JPEG-enc

Description: JPEG Encoder,Here is a quite detailed low level design document for the Core: Low Level Design Document
Platform: | Size: 796672 | Author: mahmoud | Hits:

[File Format] 17bit_Smart_Absolute_Encoder

Description: 多摩川17bit绝对值编码器的NRG协议文档，配合上传的解码源程序，采用半双工的通信模式。-Tamagawa 17bit absolute encoder NRG agreement documents, with the upload source decoder, using half-duplex communication mode.
Platform: | Size: 4419584 | Author: 王中超 | Hits:

[VHDL-FPGA-Verilog] vhdl

Description: ldpc编码的vhdl的实现，一种802.13的方式-ldpc coding vhdl implementation, a 802.13 a way
Platform: | Size: 6144 | Author: lq | Hits:

[Software Engineering] encoder

Description: 此为介绍一光电编码器的学术论文，采用VHDL语言编写，介绍了4分频的实现。-This is the description of the papers of a photoelectric encoder using VHDL language, introduced a 4-band implementation.
Platform: | Size: 108544 | Author: name | Hits:

[VHDL-FPGA-Verilog] coder_counter

Description: 增量式光电编码器计数器的FPGA实现程序,verilog3段式FSM,异步加载.-Incremental Optical Encoder counter program FPGA implementation, verilog3 struts FSM, asynchronous load.
Platform: | Size: 1024 | Author: | Hits:

[VHDL-FPGA-Verilog] FPGA-convolutions-encoder

Description: 卷积码是数字通信中很重要的一种差错控制编码具有很好的性能,用硬件的形式描述具有速度快，便于修改的优点，通过该种方法设，计的编码器经测试运行可靠正确。-Convolutional codes are very important in digital communication error control coding with a good performance, with the description of the hardware in the form of a fast, easy to modify the benefits set by the methods, namely, the encoder has been tested and reliable operation correctly .
Platform: | Size: 4096 | Author: will li | Hits:

[VHDL-FPGA-Verilog] Bch15_7

Description: BCH ENCODER DECODER -BCH ENCODER DECODER
Platform: | Size: 7168 | Author: pradeep | Hits:

[VHDL-FPGA-Verilog] encoder-based-on-Gray-code

Description: 基于VHDL格雷码编码器的设计，可以在试验箱上直接运行-Design of VHDL encoder based on Gray code, can be run directly in the chamber
Platform: | Size: 64512 | Author: 漆广文 | Hits:

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[Other resource] VHDL范例

[Other resource] encoder

[VHDL-FPGA-Verilog] simple h264 vhdl encoder

[SCM] VHDL范例

[VHDL-FPGA-Verilog] encoder

[VHDL-FPGA-Verilog] mancheester_v

[SCM] CPLD

[VHDL-FPGA-Verilog] vhdl

[VHDL-FPGA-Verilog] CRC16bits

[VHDL-FPGA-Verilog] s3esk_rotary_encoder_interface

[source in ebook] HammingDecoder

[VHDL-FPGA-Verilog] mux4

[VHDL-FPGA-Verilog] vhdl-JPEG-enc

[File Format] 17bit_Smart_Absolute_Encoder

[VHDL-FPGA-Verilog] vhdl

[Software Engineering] encoder

[VHDL-FPGA-Verilog] coder_counter

[VHDL-FPGA-Verilog] FPGA-convolutions-encoder

[VHDL-FPGA-Verilog] Bch15_7

[VHDL-FPGA-Verilog] encoder-based-on-Gray-code

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